In graphics processing, much data is managed in order to provide a resultant image on a computer display. One form of such data includes vertex data that comprises information for displaying triangles, lines, points or any other type of portions of an image on the computer display. Prior Art Table 1 includes an example of typical vertex data.
Prior Art Table 1position(X Y Z W)diffuse(R G B A)specular(R G B F)texture0(S T R Q)texture1(S T R Q)
Together, multiple sets of such vertex data are used to represent one of the portions of the image. In order to accomplish this, each vertex, on average, requires 40 bytes of memory storage space. During conventional system operation, over 10 million vertexes are typically exchanged every second during processing. This results in a data transfer rate of 400 MB/s.
During the processing of vertex data, various components of a system come into play. Prior Art FIG. 1 illustrates an example of a system 100 that processes vertex data. As shown, included are a processor 102, system memory 104, a graphics accelerator module 106, and a bus 108 for allowing communication among the various components.
In use, the processor 102 locates the vertex data in the system memory 104. The vertex data is then routed to the processor 102, after which the vertex data is copied for later use by the graphics accelerator module 106. The graphics accelerator module 106 may perform various operations such as transform and/or lighting operations on the vertex data.
As mentioned earlier, a typical data transfer rate of 400 MB/s is required in current systems to process the vertex data. During the transfer of such data in the system 100 of Prior Art FIG. 1, the bus 108 connecting the processor 102 and the graphics accelerator module 106 is required to handle an input data transfer rate of 400 MB/s along with an output data transfer rate of 400 MB/s.
As such, the foregoing bus 108 must accommodate a data transfer rate of 800 MB/s while handling the vertex data. Conventionally, such bus 108 is 64 bits wide and the processor 102 runs at about 100 MHz. Therefore, the bus 108 is often strained during use in the system 100 of Prior Art FIG. 1. Further, with data transfer rates constantly rising, processors will soon not be able to be used to copy vertex data.
There is therefore a need for a system that allows direct memory access to vertex data while bypassing the processor in order to avoid overloading the processor and associated bus.